Non-volatile memory devices, such as EPROM, EEPROM, and Flash EEPROM, store data even after power is turned off. One common application of EEPROMs is in programmable logic devices (PLDs). PLDs are standard semiconductor components purchased by systems manufacturers in a “blank” state that can be custom configured into a virtually unlimited number of specific logic functions. PLDs provide system designers with the ability to quickly create custom logic functions to provide product differentiation without sacrificing rapid time to market. PLDs may be reprogrammable, meaning that the logic configuration can be modified after the initial programming.
A type of PLD called a complex programmable logic device (CPLD) is shown in FIG. 1. A CPLD 10 includes a plurality of generic logic blocks (GLB), such as GLB 12. The GLBs are in groups of four within segments, such as segment 14. Each segment includes a local segment switching matrix (SSM), such as shown at 16. The SSM allows for programmable routing of signals between the GLBs. A global switching matrix (GSM) 18 allows for programmable interconnection between the segments. Four I/O banks 20 allow connection to pins (not shown) on the outside of the CPLD.
Within each GLB 12 are a plurality of programmable macrocells. Macrocells are well known in the art, an example of which is shown and described in U.S. Pat. No. 6,255,847 (the '847 patent). The macrocell described therein is capable of performing two logic functions, or dual logic functions, concurrently within a single macrocell.
Certain limitations exist on the use of dual logic macrocells. For instance, if each of two functions requires the use of a register to store its output signal, these two functions may not be performed by the same macrocell. Likewise, if each of two functions requires the introduction of product terms from adjacent macrocells via a product term sharing array, the two functions may not be performed by the same macrocell.
Because restrictions exist on the use of macrocells for more than one logic function, and because the full range of such limitations has not been discerned, in practice these dual function macrocells have been programmed for providing only one logic function at a given time.
It is, therefore, desirable to provide a methodology that allows for programming of multi-function macrocells so that more than one logic function may be utilized concurrently.